Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■NESA-FO register
Target PC-H98
Chip NESA-FO
Explanation o The PC-H98 series uses an architecture named NESA (New Extended
Standard Architecture). NESA is mainly a bus architecture, but has a mechanism
for unified resource management.
o The expansion slot (NESA slot) of a NESA-equipped machine has a C bus
connector for using conventional option boards, and an E bus connector for
using NESA-compatible option boards.
Figure 1: Structure of the NESA slot
--------------------------------------------------------------
+--------------------+ +--------------------+
| E bus | | E bus |
+--------------------+ +--------------------+
+-------------------------------------------+
-- | C bus | --
-- +-------------------------------------------+ -- Board surface
* The E bus connector and C bus connector of the NESA slot are at different
physical heights from the board surface, and C bus option boards are
inserted into the card edge connector, while NESA-compatible boards are
connected to the E bus connector.
* Usually, when people simply say NESA bus, they are referring to the signal
coming out of the E bus connector.
--------------------------------------------------------------
o NESA-FO (New Extended Standard Architecture-Flexible Option) is a mechanism
for uniformly configuring the environment of various hardware connected to the
NESA bus from software. NESA-FO eliminates the need for configuration using
dip switches, etc., and provides a function for automatically configuring the
hardware environment using SSP (System Setup Program) and ASP (Auto Setup Program).
o NESA-FO registers are mapped to the I/O space of the CPU. The mapping
address is uniquely determined for each expansion slot, hard disk slot, and
built-in device, so there is no conflict between NESA-FO registers themselves.
Even if multiple NESA-compatible boards of the same type are installed, it is
possible to reliably access the desired board. The NESA-FO registers
themselves use 8xDnh and 8xEnh in the I/O space, that is, the user-free I/O
address space.
Table 1: NESA-FO register mapping
----------------------------------------------------------------
15 8 7 0
I/O address 1000 nnnn mmmm xxxx
| | |
| | +-------- Register number
| +------------- Corresponds to physical slot
+------------------ Corresponds to device type
----------------------------------------------------------------
Table 2: Correspondence between physical slot number and slot
---------------------+----------------------------------
Physical slot number | Slot name
---------------------+----------------------------------
00h | Missing number
01h | Expansion slot #1
02h | Expansion slot #2
03h | Expansion slot #3
04h | Expansion slot #4
05h | Reserved
06h | HDC dedicated slot
07h | CRTC dedicated slot
08-0Eh | Reserved
0Fh | I/O expansion unit (Undocumented)
---------------------+----------------------------------
Table 3: Correspondence between device type value and device type
---------------------+----------------------------------
Device type value | Device type
---------------------+----------------------------------
1101b | Main unit built-in system dedicated slot
1110b | Extension box option slot
---------------------+----------------------------------
o The NESA architecture allows the use of the following I/O space for I/O
slaves of conventional C-bus option boards and for NESA bus (E-bus) option boards.
Table 4: I/O addresses available for use as C-bus I/O slaves on NESA-equipped machines
----------------------------
xnD0-xnDFh
xnE0-xnEFh
* n is 0000-0111b
* x is Don't care
----------------------------
Table 5: I/O addresses available for use as NESA option board I/O slaves
----------------------------
mnD0-mnDFh
mnE0-mnEFh
* n is 1001-1111b
* m is 0000-0111b
----------------------------
o The free I/O addresses for various option boards in the NESA architecture are listed below.
Table 6: I/O addresses available for use as I/O slaves
-------------------------------------------------------------
xnD0-xnDFh Free for C bus I/O slaves
xnE0-xnEFh Free for C bus I/O slaves
8mD0-8mDFh NESA-FO registers
8mE0-8mEFh NESA-FO registers
9nD0-9nDFh Free for NESA bus I/O slaves
9nE0-9nEFh Free for NESA bus I/O slaves
AnD0-AnDFh Free for NESA bus I/O slaves
AnD0-AnDFh Free for NESA bus I/O slaves
BnD0-BnDFh Free for NESA bus I/O slaves
BnD0-BnDFh Free for NESA bus I/O slaves
CnD0-CnDFh Free for NESA bus I/O slaves
CnD0-CnDFh Free for NESA bus I/O slaves
DnD0 to DnDFh Free for NESA bus I/O slaves
DnD0 to DnDFh Free for NESA bus I/O slaves
EnD0 to EnDFh Free for NESA bus I/O slaves
EnD0 to EnDFh Free for NESA bus I/O slaves
FnD0 to FnDFh Free for NESA bus I/O slaves
FnD0 to FnDFh Free for NESA bus I/O slaves
* x is Don't care
* n is 0000 to 0111b
* m is basically 0000 to 0111b. However, the interface of the NESA-FO
registers of NESA devices other than option boards is similar, so m can also
take the value of 1000 to 1111b.
-------------------------------------------------------------
Related 0000:0458h bit 7
INT 1Fh - Functions C0h
INT 1Fh - Functions C1h
INT 1Fh - Functions C2h
INT 1Fh - Functions C3h
INT 1Fh - Functions C4h
INT 1Fh - Functions C5h
INT 1Fh - Functions C6h
INT 1Fh - Functions C7h
I/O 8nm0h
Name NESA-FO register 0
Function
■[E^2PROM, PROM, FD media]
[READ] Read register 0 (Function ID 1)
bits 7-0: Board manufacturer code 1
[WRITE] None
■[PAL]
[READ] None
[WRITE] Write register 0 (Function ID 1)
Explanation o Reads and writes NESA-FO register 0.
o Indicates the lower 8 bits of the board manufacturer code.
Related I/O 8nm2h
I/O 8nm1h
Name NESA-FO register 1
Function
■[E^2PROM]
[READ] Register 1 read (data load register)
bit 7: EDO Data output from E^2PROM
bit 6: ECL Clock input for E^2PROM
bit 5: ECS Chip select
bit 4: EDI Data input
bit 3-0: Unused (0000b)
[WRITE] Register 1 write (data load register)
bit 7: 0
bit 6: ECL Clock input for E^2PROM
bit 5: ECS Chip select
bit 4: EDI Data input
bit 3-0: Unused (0000b)
■[PROM]
[READ] Register 1 read (data load register)
bit 7-0: ROM/PAL read data
[WRITE] Register 1 write (data load register)
bit 7: ACC NESA-FO address counter reset
1 = Reset pulse is sent to the counter
0 = Normal
Bits 6-0: Unused (000000b)
■[FD medium]
[READ] Read register 1 (data load register)
[WRITE] Write register 1 (data load register)
■[PAL]
[READ] Read register 1 (setup data read byte 1)
[WRITE] None [PAL]
Explanation o Reads and writes NESA-FO register 1.
Related I/O 8nm0h
I/O 8nm2h
Name NESA-FO register 2
Function
■[E^2PROM,PROM,FD media]
[READ] Read register 2 (Function ID2)
bit 7-0: Board manufacturer code 2
* Board manufacturer code 1,2 is the board manufacturer name (uppercase 3
letters) converted to ASCII code and compressed to 2 bytes. Board
manufacturer code for general users 6C00h-6FFFh
[WRITE] None
■[PAL]
[READ] None
[WRITE] Write register 2 (Function ID2)
Explanation o Reads and writes NESA-FO register 2.
o Indicates the upper 8 bits of the board manufacturer code.
Related I/O 8nm0h
I/O 8nm3h
Name NESA-FO register 3
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Write register 3
■[PAL]
[READ] Read register 3 (setup data read byte 2)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 3.
Related
I/O 8nm4h
Name NESA-FO register 4
Function
■[E^2PROM,PROM,FD media]
[READ] Read register 4 (function ID3)
Bits 7-0: Product code
Product code that corresponds one-to-one to the board
The product codes for NEC's NESA devices are as follows.
Table Example of product code and product name correspondence (Undocumented)
-------------+-----------------------------
Product code | Product name
-------------+-----------------------------
02h | PC-H98/70-E02(ESDI 100MB HDD)
03h | PC-H98S/8-E02(SCSI 100MB HDD)
04h | PC-H98-B02(2MB memory board)
-------------+-----------------------------
[WRITE] None
■[PAL]
[READ] None
[WRITE] Register 4 write (Function ID3)
Explanation o Reads and writes to NESA-FO register 4.
o Indicates the product code corresponding to the board.
Related
I/O 8nm5h
Name NESA-FO register 5
Function
■[E^2PROM, PROM, FD media]
[READ] None
[WRITE] Write to register 5
■[PAL]
[READ] Read from register 5 (setup data read byte 3)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 5.
Related
I/O 8nm6h
Name NESA-FO register 6
Function
■[E^2PROM,PROM,FD media]
[READ] Read register 6 (Function ID4)
Bits 7-4: Comp code
* Board revision version
Bits 3,2: Board classification
11b = Not implemented
10b = Reserved
01b = New board (NESA board)
00b = Conventional board (C bus)
Bits 1,0: Setup information type
11b = E^2PROM
10b = PROM
01b = PAL
00b = FD media or no information
[WRITE] None
■[PAL]
[READ] None
[WRITE] Write register 6 (Function ID4)
Explanation o Reads and writes to NESA-FO register 6.
Related
I/O 8nm7h
Name NESA-FO register 7
Function
■[E^2PROM, PROM, FD media]
[READ] None
[WRITE] Write to register 7
■[PAL]
[READ] Read from register 7 (setup data read byte 4)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 7.
Related
I/O 8nm8h
Name NESA-FO register 8
Function
[READ] Register 8 read (board control)
bit 7,6: EINT1,EINT0 interrupt level sense
bit 5,4: INT1,INT0 interrupt level sense (for external use)
1 = When a level interrupt occurs
0 = No level interrupt occurs (at reset)
* Senses the level of each channel of the interrupt request signal IN<1,0>
input from the device on the option board.
bit 3: NMI NMI sense
0 = Normal (NMI not occurring at reset)
1 = NMI occurring
bit 2,1: WAIT1,0 NESA-FO register wait setting
00 = 0 wait (at reset)
01 = 1 wait
10 = 2 waits
11 = 3 waits
* Specifies the addition of a wait cycle. However, wait specification to the
BIOS ROM is excluded.
bit 0: BDE board enable
0 = Disable (at reset)
1 = Enable
[WRITE] Write register 8 (board control)
bit 7-4: Unused
bit 3: NMI NMI sense
0 = NMI clear
1 = NMI save
bit 0: BDE board enable
0 = Disable
1 = Enable
* Enables/disables board functions except for access to NESA-FO registers.
Description o Reads and writes to NESA-FO register 8.
Related
I/O 8nm9h
Name NESA-FO register 9
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Write register 9
■[PAL]
[READ] Read register 9 (setup data read byte 5)
[WRITE] None
Description o Reads and writes to NESA-FO register 9.
Related
I/O 8nmAh
Name NESA-FO register A
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Write register 10
■[PAL]
[READ] None
[WRITE] Write register 10 (DMA, interrupt, number of waits)
bit 7-5: A2-0 Unknown
* Loopback port, does not function with NESA-FO chip
bit 4: INTE/L Interrupt request method
0 = Level (at reset)
1 = Edge
* Sets whether the interrupt request signal IN<1,0> input from the device on
the option board is requested by edge or level.
bit 3,2: INTCH11,INTCH10
bit 1,0: INTCH01,INTCH00
00b = IR0 (at reset, both channels)
01b = IR1
10b = IR2
11b = IR3
* Sets which terminal of the interrupt request signal group IR<3-0> that
outputs the interrupt request signal IN<1,0> input from the device on the
option board to the NESA bus side.
Explanation o Reads and writes to NESA-FO register 10.
Related
I/O 8nmBh
Name NESA-FO register B
Function
■[E^2PROM,PROM,FD medium]
[READ] None
[WRITE] Write to register 11
■[PAL]
[READ] Read register 11 (setup data read byte 6)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 11.
I/O 8nmCh
Name NESA-FO Register C
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Register 12 write
■[PAL]
[READ] None
[WRITE]
bit 7: IOCS
0 = PA<F~C>/ADE decode (at reset)
(Address 0nmXh X:0~F→ICS active)
1 = PAF/ADE decode
(Address inmXh i:0~7,X:0~F→ICS active)
* Sets the decode condition of the I/O chip select signal (ICS) output to the
I/O device on the option board.
bit 6,5: BWAIT1,BWAIT0
00b = 0 wait
01b = 1 wait
10b = 2 wait
11b = 3 wait (at reset)
* Specifies the addition of a wait cycle when reading the BIOS ROM.
bit 4: DMAIORW
0 = Enable (at reset)
1 = Disable
* Specifies whether to enable or disable IOR/IOW output during DMA.
bit 3,2: DMATR11,DMATR10 DMA transfer mode (for DMA ch#1)
bit 1,0: DMATR01,DMATR00 DMA transfer mode (for DMA ch#0)
00b = Byte transfer mode (at reset)
01b = Word transfer mode
10b = Double word transfer mode
11b = Disable (DMA transfer is not performed)
* Sets the transfer mode (byte/word/double word) for each channel of the DMA
request signal DR<1,0> input from the device on the option board.
The transfer mode of a channel that does not request DMA must match the
transfer mode of a channel that does.
Description o Reads and writes to NESA-FO register 12.
I/O 8nmDh
Name NESA-FO register D
Function
■[E^2PROM, PROM, FD media]
[READ] None
[WRITE] Write to register 13
■[PAL]
[READ] Read from register 13 (setup data read byte 7)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 13.
I/O 8nmEh
Name NESA-FO register E
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Write register 14
■[PAL]
[READ] None
[WRITE] None
bit 7,6 :B1,B0 Unknown
* Loopback port, does not function with NESA-FO chips
bit 5-3: DMACH12-10
bit 2-0: DMACH02-00
000b = RQ0
001b = RQ1
010b = RQ2
011b = RQ3
100b = RQ4
101b = RQ5
110b = RQ6
111b = Setting prohibited
* Specifies which terminal of the DMA request signal group RQ<6-0> that
outputs the DMA request signal DR<1,0> input from the device on the option
board side is connected to.
Explanation o Reads and writes to NESA-FO register 14.
Related
I/O 8nmFh
Name NESA-FO register F
Function
■[E^2PROM,PROM,FD media]
[READ] None
[WRITE] Write to register 15
■[PAL]
[READ] Read from register 15 (setup data read byte 8)
[WRITE] None
Explanation o Reads and writes to NESA-FO register 15.
Related